1. Field of the Invention
The present invention relates generally to a current switching type switch circuit to be used for an analog/digital converter or so forth. More specifically, the invention relates to a current switching type switch circuit which can make an operation voltage of a current load circuit greater in a low power source voltage.
2. Description of the Prior Art
Conventionally, a current switching type switch circuit in a flip-flop and a sample hold circuit which are constructed by bipolar transistors has a pair of transistors controlled by a clock and a constant current source. Such switch circuit has been disclosed in Toyoki TAKEMOTO et al., "A Fully Parallel 10-Bit A/D Converter with Video Speed", IEEE JOURNAL OF SOLID STATE CIRCUIT, VOL. SC-17, No. 6, December 1982, pp. 1133-1138, and Akira MATSUZAWA et al., "An 8b 600 MHz Flash A/D Converter with Multistage Duplex Gray Coding", ICD91-86, pp. 37-42.
FIG. 1 is a circuit diagram showing the conventional current switching type switch circuit. As shown in FIG. 1, a first load circuit 5 and a second load circuit 6 are connected to a first power source 21 in parallel. These first and second load circuits 5 and 6 are connected to a current switching type switch circuit 54. The switch circuit 54 is constructed with npn bipolar transistors Q1 and Q2 and a constant current source 51. Namely, collectors of the transistors Q1 and Q2 are connected to the first and second load circuits 5 and 6, respectively. On the other hand, emitters of the npn bipolar transistors Q1 and Q2 are connected in common and to a second power source 22 via the constant current power 51. Furthermore, the bases of the bipolar transistors Q1 and Q2 are connected to clock signal input terminals 31 and 32, respectively.
In the switch circuit 54 constructed as set forth above, a non-inverted clock signal CLK2 and an inverted clock signal CLK2B having complementary relationship are input to the bipolar transistors from clock signal input terminals 31 and 32. Then, either one of the bipolar transistors Q1 and Q2 is turned ON and the other is turned OFF. By this, a current of the constant current source 51 flows through the first load circuit 5 or the second load circuit 6. Thus, the current of the constant current source 51 is supplied to different supply destination by switching the clock signal.
The conventional current switching type switch circuit shown in FIG. 1 has vertically stacked construction. The operation voltage Vd to be applied to the first and second load circuits 5 and 6 can be expressed by the following equation (1). EQU Vd=Vcc1-Vcc2-(Vce+VI) (1)
In the equation (1), Vcc1 is a power source voltage of a first power source 21, and Vcc2 is a power source voltage of a second power source 22. Also, Vce is a voltage between collector and emitter of bipolar transistor, and VI is a voltage required for a constant current source 51. As expressed by the foregoing equation (1), when the power source voltage (Vcc1 -Vcc2) becomes lower, an operation voltage Vd to be applied to the load circuit also becomes lower. As a result, problems, such as lowering of operation frequency of the load circuit or narrowing of dynamic range are caused. Further detailed discussion will be given with respect to the problems.
FIG. 2 is a circuit diagram showing a comparator, to which the conventional current switching type switch circuit is applied, to be used in a high speed A/D converter or the like. FIG. 3 is a diagrammatic illustration showing an analog voltage to be input through a voltage input terminal. As shown in FIG. 2, the comparator is constructed with a constant current sources 52 and 53, bipolar transistors Q5, Q6, Q7, Q8, Q9 and Q10, resistors R1 and R2 and a switch circuit 54. Namely, collectors of the bipolar transistors Q5 and Q6 are connected to a first power source 21, bases thereof are respectively connected to voltage input terminals 33 and 34. Voltages of Vin1 and Vin2 are input to the input terminals 33 and 34, respectively. Also, emitters of the bipolar transistors Q5 and Q6 are connected to bases of the bipolar transistors Q8 and Q7, respectively, and in conjunction therewith, to the second power source 22 via constant current sources 52 and 53.
One end portions of the resistors R1 and R2 are connected to the first power source 21 in parallel. The other end of the resistor R1 is connected to a collector of the bipolar transistor Q7, a collector of the bipolar transistor Q9 and a base of the bipolar transistor Q10, and further to a voltage output terminal 35. On the other hand, the other end of the resistor R2 is connected to a collector of the bipolar transistor Q8, a base of the bipolar transistor Q9 and a collector of the bipolar transistor Q10, and further to a voltage output terminal 36.
Emitters of the bipolar transistors Q7 and Q8 are connected in common and to a collector of the bipolar transistor Q1 which forms the switch circuit 54. Emitters of the bipolar transistors Q9 and Q10 are connected in common and to a collector of the bipolar transistor Q2 which also forms the switch circuit 54.
In the comparator constructed as set forth above, when the clock signal CLK2 input through the clock signal input terminal 31 is HIGH, a current I flows through a differential amplifier formed by the bipolar transistors Q7 and Q8 and so forth. By this, fine input potential difference (Vin1-Vin2) is amplified. Subsequently, when the clock signal CLK2B input from the clock signal input terminal 32 turns HIGH, the input potential difference (Vin1-vin2) is amplified up to a digital level by a latch circuit formed by the bipolar transistors Q9 and Q10.
In FIG. 2, assuming that a base-emitter voltage of the bipolar transistor is Vbe, a lower limit Vmin of the input voltage is expressed by the following equation (2). EQU Vmin=2Vbe+Vce+VI (2)
On the other hand, assuming that a dynamic range of an analog voltage input is Vfc, and an upper limit of the input voltage is the power source voltage Vcc1, Vcc1 is expressed by the following equation (3). ##EQU1##
In the equations (2) and (3), Vbe, Vce and VI are expressed by the following expressions (4), (5) and (6). EQU Vbe.apprxeq.0.8(V) (4) EQU Vce.gtoreq.0.5(V) (5) EQU VI.gtoreq.0.6(V) (6)
Replacing the foregoing equation (2) with the expressions (4) to (6), the lower limit Vmin of the input voltage becomes greater than or equal to 2.7(V). Accordingly, when the power source voltage Vcc1 is 5.0(V), the dynamic range Vfc can be 2.3(V), whereas the power source voltage Vcc1 is 3.0(V), the dynamic range Vfc becomes 0.3(V).
FIG. 4 is a waveform chart showing waveforms of an input voltage, the clock signal and an output voltage corresponding thereto with taking voltage in vertical axis and time in horizontal axis. It should be noted that FIG. 4 shows waveforms in the case where the power source voltage Vcc1 is 3.0(V). As shown in FIG. 4, when the voltage input through the input terminal 33 is set at about 3.0(V), the dynamic range Vfc becomes 0.3(V), a digital voltage corresponding to the input voltage is output. However, when the input voltage is set about 2.5(V), it becomes impossible to output the normal digital level voltage.